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MCF5271 Integrated Microprocessor Hardware Specification
by: Microcontroller Solutions Group
The MCF5271 family is a highly integrated implementation of the ColdFire(R) family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent features and functions of the MCF5271 family. The MCF5271 family includes the MCF5271 and MCF5270 microprocessors. The differences between these parts are summarized below in Table 1. This document is written from the perspective of the MCF5271 and unless otherwise noted, the information applies also to the MCF5270. The MCF5271 family combines low cost with high integration on the popular version 2 ColdFire core with over 144 (Dhrystone 2.1) MIPS at 150 MHz. Positioned for applications requiring a cost-sensitive 32-bit solution, the MCF5271 family features a 10/100 Ethernet MAC and optional hardware encryption to ensure the application can be connected and protected. In addition, the MCF5271 family features an enhanced multiply accumulate unit (eMAC), large on-chip memory (64 Kbytes SRAM, 8 Kbytes configurable cache), and a 32-bit SDR SDRAM memory controller.
Contents
1 2 3 4 5 6 7 8 9 MCF5271 Family Configurations . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 8 Mechanicals/Pinouts and Part Numbers . . . . . . . . . . . . 12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document Revision History . . . . . . . . . . . . . . . . . . . . . . 39
(c) Freescale Semiconductor, Inc., 2009. All rights reserved.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Freescale Semiconductor Data Sheet: Technical Data
Document Number: MCF5271EC Rev. 4, 08/2009
MCF5271 Family Configurations
1
MCF5271 Family Configurations
Table 1. MCF5271 Family Configurations
Module ColdFire V2 Core with EMAC and Hardware Divide System Clock Performance (Dhrystone/2.1 MIPS) Instruction/Data Cache Static RAM (SRAM) Interrupt Controllers (INTC) Edge Port Module (EPORT) External Interface Module (EIM) 4-channel Direct-Memory Access (DMA) SDRAM Controller Fast Ethernet Controller (FEC) Hardware Encryption Watchdog Timer (WDT) Four Periodic Interrupt Timers (PIT) 32-bit DMA Timers QSPI UART(s) I2C General Purpose I/O Module (GPIO) JTAG - IEEE 1149.1 Test Access Port Package
2 x x x x x -- x x 4 x 3 x x x
MCF5270
x
MCF5271
x
150 MHz 144 8 Kbytes 64 Kbytes 2 x x x x x x x x 4 x 3 x x x
160 QFP, 160 QFP, 196 MAPBGA 196 MAPBGA
2
Block Diagram
The superset device in the MCF5271 family comes in a 196 mold array plastic ball grid array (MAPBGA) package. Figure 1 shows a top-level block diagram of the MCF5271.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 2 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Block Diagram Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
SDRAMC QSPI
EIM (To/From SRAM backdoor) CHIP SELECTS
I2C_SDA I2C_SCL UnTXD UnRXD UnRTS
EBI Arbiter INTC0 INTC1 PADI - Pin Muxing
UnCTS DTnOUT DTnIN FEC
(To/From PADI)
FAST ETHERNET CONTROLLER (FEC)
UART 0
UART 1
UART 2
I2 C
QSPI
SDRAMC
D[31:0]
(To/From PADI) (To/From PADI)
4 CH DMA
DTIM 0
DTIM 1
DTIM 2
DTIM 3
A[23:0] R/W CS[3:0] TA
DREQ[2:0] DACK[2:0]
MUX
TSIZ[1:0]
BDM
JTAG_EN
V2 ColdFire CPU
DIV EMAC
TEA BS[3:0]
JTAG TAP 64 Kbytes SRAM (8Kx16)x4 8 Kbytes CACHE (1Kx32)x2 PORTS (GPIO)
CIM
Watchdog Timer
(To/From Arbiter)
SKHA
PLL CLKGEN (To/From INTC)
PIT0
PIT1
PIT2
PIT3
RNGA
MDHA Cryptography Modules
Edge Port
Figure 1. MCF5271 Block Diagram
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 3
Features
3 4
Features Signal Descriptions
For a detailed feature list see the MCF5271 Reference Manual (MCF5271RM).
This section describes signals that connect off chip, including a table of signal properties. For a more detailed discussion of the MCF5271 signals, consult the MCF5271 Reference Manual (MCF5271RM).
4.1
Signal Properties
Table 4 lists all of the signals grouped by function. The "Dir" column is the direction for the primary function of the pin. Refer to Section 6, "Mechanicals/Pinouts and Part Numbers," for package diagrams. NOTE In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. MCF5270 and MCF5271 Signal Information and Muxing
Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA
Reset RESET RSTOUT -- -- -- -- -- -- Clock EXTAL XTAL CLKOUT -- -- -- -- -- -- -- -- -- Mode Selection CLKMOD[1:0] RCON -- -- -- -- -- -- I I 20,21 79 G5,H5 K10 I O O 86 85 89 M14 N14 K14 I O 83 82 N13 P13
External Memory Interface and Ports A[23:21] PADDR[7:5] CS[6:4] -- O 126, 125, 124 B11, C11, D11
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 4 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Signal Descriptions
Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)
Signal Name A[20:0] GPIO -- Alternate 1 Alternate 2 Dir.1 -- -- O MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA
123:115, A12, B12, C12, 112:106, 102:98 A13, B13, B14, C13, C14, D12, D13, D14, E11, E12, E13, E14, F12, F13, F14, G11, G12, G13 22:30, 33:39 G1, G2, H1, H2, H3, H4, J1, J2, J3, J4, K1, K2, K3, K4, L1, L2 M1, N1, M2, N2, P2, L3, M3, N3 P3, M4, N4, P4, L5, M5, N5, P5 B6, C6, D7, C7 N6 H11 J14 J13 P6 P7 H13 H12
D[31:16]
--
--
--
O
D[15:8] D[7:0] BS[3:0] OE TA TEA R/W TSIZ1 TSIZ0 TS TIP
PDATAH[7:0] PDATAL[7:0] PBS[7:4] PBUSCTL7 PBUSCTL6 PBUSCTL5 PBUSCTL4 PBUSCTL3 PBUSCTL2 PBUSCTL1 PBUSCTL0
-- -- CAS[3:0] -- -- DREQ1 -- DACK1 DACK0 DACK2 DREQ0
-- -- -- -- -- -- -- -- -- -- -- Chip Selects
O O O O I I O O O O O
42:49 50:52, 56:60 143:140 62 96 -- 95 -- -- 97 --
CS[7:4] CS[3:2] CS1 CS0
PCS[7:4] PCS[3:2] PCS1 --
-- SD_CS[1:0] -- --
-- -- -- --
O O O O
-- 132,131 130 129
B9, A10, C10, A11 A9, C9 B10 D10
SDRAM Controller SD_WE SD_SCAS SD_SRAS SD_CKE PSDRAM5 PSDRAM4 PSDRAM3 PSDRAM2 -- -- -- -- -- -- -- -- -- -- O O O O O 92 91 90 -- -- K13 K12 K11 E8 L12, L13
SD_CS[1:0] PSDRAM[1:0]
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 5
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Signal Descriptions
Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA
External Interrupts Port IRQ[7:3] IRQ2 IRQ1 PIRQ[7:3] PIRQ2 PIRQ1 -- DREQ2 -- -- -- -- FEC EMDC EMDIO ECOL ECRS ERXCLK ERXDV ERXD[3:0] ERXER ETXCLK ETXEN ETXER ETXD[3:0] PFECI2C3 PFECI2C2 -- -- -- -- -- -- -- -- -- -- I2C_SCL I2C_SDA -- -- -- -- -- -- -- -- -- -- U2TXD U2RXD -- -- -- -- -- -- -- -- -- -- I2C I2C_SDA I2C_SCL PFECI2C1 PFECI2C0 -- -- -- -- DMA DACK[2:0] and DREQ[2:0] do not have a dedicated bond pads. Please refer to the following pins for muxing: TS and DT2OUT for DACK2, TSIZ1and DT1OUT for DACK1, TSIZ0 and DT0OUT for DACK0, IRQ2 and DT2IN for DREQ2, TEA and DT1IN for DREQ1, and TIP and DT0IN for DREQ0. QSPI QSPI_CS1 QSPI_CS0 QSPI_CLK QSPI_DIN QSPI_DOUT PQSPI4 PQSPI3 PQSPI2 PQSPI1 PQSPI0 SD_CKE -- I2C_SCL I2C_SDA -- -- -- -- -- -- O O O I O 139 146 147 148 149 B7 A6 C5 B5 A5 -- -- I/O I/O -- -- J12 J11 O I/O I I I I I O I I O O 151 150 9 8 7 6 5:2 159 158 157 156 155:152 D4 D5 E2 E1 D1 D2 D3, C1, C2, B1 B2 A2 C3 B3 A3, A4, C4, B4 I I I IRQ7=63 IRQ4=64 -- 65 N7, M7, L7, P8, N8 M8 L8
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 6 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Signal Descriptions
Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA
UARTs U2TXD U2RXD U1CTS U1RTS U1TXD U1RXD U0CTS U0RTS U0TXD U0RXD PUARTH1 PUARTH0 PUARTL7 PUARTL6 PUARTL5 PUARTL4 PUARTL3 PUARTL2 PUARTL1 PUARTL0 -- -- U2CTS U2RTS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DMA Timers DT3IN DT3OUT DT2IN DT2OUT DT1IN DT1OUT DT0IN DT0OUT PTIMER7 PTIMER6 PTIMER5 PTIMER4 PTIMER3 PTIMER2 PTIMER1 PTIMER0 U2CTS U2RTS DREQ2 DACK2 DREQ1 DACK1 DREQ0 DACK0 QSPI_CS2 QSPI_CS3 DT2OUT -- DT1OUT -- -- -- BDM/JTAG2 DSCLK PSTCLK BKPT DSI DSO JTAG_EN DDATA[3:0] PST[3:0] -- -- -- -- -- -- -- -- TRST TCLK TMS TDI TDO -- -- -- -- -- -- -- -- -- -- -- O O O I O I O O 70 68 71 73 72 78 -- 77:74 N9 P9 P10 M10 N10 K9 M12, N12, P12, L11 M11, N11, P11, L10 I O I O I O I O -- -- 66 -- 61 -- 10 11 H14 G14 M9 L9 L6 M6 E4 F4 O I I O O I I O O I -- -- 136 135 133 134 12 15 14 13 A8 A7 B8 C8 D9 D8 F3 G3 F1 F2
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 7
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Design Recommendations
Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA
Test TEST PLL_TEST -- -- -- -- -- -- Power Supplies VDDPLL VSSPLL OVDD -- -- -- -- -- -- -- -- -- I I I 87 84 M13 L14 I I 19 -- F5
1, 18, 32, 41, 55, E5, E7, E10, F7, 69, 81, 94, 105, F9, G6, G8, H7, 114, 128, 138, H8, H9, J6, J8, 145 J10, K5, K6, K8 17, 31, 40, 54, A1, A14, E6, E9, 67, 80, 88, 93, F6, F8, F10, G7, 104, 113, 127, G9, H6, J5, J7, 137, 144, 160 J9, K7, P1, P14 16, 53, 103 D6, F11, G4, L4
VSS
--
--
--
I
VDD
1
--
--
--
I
Refers to pin's primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM. 2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
5
5.1
* * *
Design Recommendations
Layout
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power and ground planes for the MCF5271. See application note AN1259, System Design and Layout Techniques for Noise Reduction in Processor-Based Systems. Match the PC layout trace width and routing to match trace length to operating frequency and board impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace and separation. Clocks get extra separation and more precise balancing.
5.2
*
Power Supply
33 F, 0.1 F, and 0.01 F across each power supply
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 8 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Design Recommendations
5.2.1
Supply Voltage Sequencing and Separation Cautions
Figure 2 shows situations in sequencing the I/O VDD (OVDD), PLL VDD (VDDPLL), and Core VDD (VDD). OVDD is specified relative to VDD.
OVDD, VDDPLL Supplies Stable 2.5V
DC Power Supply Voltage
3.3V
1.5V
1
VDD
2
0 Time Notes: 1. VDD should not exceed OVDD or VDDPLL by more than 0.4 V at any time, including power-up. 2. Recommended that VDD should track OVDD/VDDPLL up to 0.9 V, then separate for completion of ramps. 3. Input voltage must not be greater than the supply voltage (OVDD, VDD, or VDDPLL) by more than 0.5 V at any time, including during power-up. 4. Use 1 ms or slower rise time for all supplies.
Figure 2. Supply Voltage Sequencing and Separation Cautions
5.2.1.1
Power Up Sequence
If OVDD is powered up with VDD at 0 V, then the sense circuits in the I/O pads cause all pad output drivers connected to the OVDD to be in a high impedance state. There is no limit on how long after OVDD powers up before VDD must power up. VDD should not lead the OVDD or VDDPLL by more than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 s to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: 1. Use 1 ms or slower rise time for all supplies. 2. VDD and OVDD/VDDPLL should track up to 0.9 V, then separate for the completion of ramps with OVDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
5.2.1.2
Power Down Sequence
If VDD is powered down first, then sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after VDD powers down before OVDD/VDDPLL must power down. VDD should not lag OVDD or VDDPLL going low by more than 0.4 V during power down or there
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 9
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Design Recommendations
will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. Drop VDD to 0 V. 2. Drop OVDD/VDDPLL supplies.
5.3
* *
Decoupling
Place the decoupling caps as close to the pins as possible, but they can be outside the footprint of the package. 0.1 F and 0.01 F at each supply input
5.4
*
Buffering
Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses when excessive loading is expected. See Section 7, "Electrical Characteristics."
5.5
*
Pull-up Recommendations
Use external pull-up resistors on unused inputs. See pin table.
5.6
* * * * * * * *
Clocking Recommendations
Use a multi-layer board with a separate ground plane. Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator pins) as possible. Do not run a high frequency trace around crystal circuit. Ensure that the ground for the bypass capacitors is connected to a solid ground trace. Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents in the vicinity of the crystal. Tie the ground pin to the most solid ground in the system. Do not connect the trace that connects the oscillator and the ground plane to any other circuit element. This tends to make the oscillator unstable. Tie XTAL to ground when an external oscillator is clocking the device.
5.7
5.7.1
5.7.1.1
Interface Recommendations
SDRAM Controller
SDRAM Controller Signals in Synchronous Mode
Table 3 shows the behavior of SDRAM signals in synchronous mode.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 10 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Design Recommendations
Table 3. Synchronous DRAM Signal Connections
Signal SD_SRAS Description Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS. Do not confuse SD_SRAS with the DRAM controller's SD_CS[1:0], which should not be interfaced to the SDRAM SD_SRAS signals. Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled SD_SCAS on the SDRAM. DRAM read/write. Asserted for write operations and negated for read operations. Row address strobe. Select each memory block of SDRAMs connected to the MCF5271. One SD_CS signal selects one SDRAM block and connects to the corresponding CS signals. Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SD_CKE to provide command-bit functionality. Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs. Bus clock output. Connects to the CLK input of SDRAMs.
SD_SCAS
DRAMW SD_CS[1:0] SD_CKE
BS[3:0] CLKOUT
5.7.1.2
Address Multiplexing
See the SDRAM controller module chapter in the MCF5271 Reference Manual for details on address multiplexing.
5.7.2
Ethernet PHY Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3 standard defines and the FEC module supports 18 signals. These are shown in Table 4.
Table 4. MII Mode
Signal Description Transmit clock Transmit enable Transmit data Transmit error Collision Carrier sense Receive clock Receive enable Receive data MCF5271 Pin ETXCLK ETXEN ETXD[3:0] ETXER ECOL ECRS ERXCLK ERXDV ERXD[3:0]
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 11
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Mechanicals/Pinouts and Part Numbers
Table 4. MII Mode (continued)
Signal Description Receive error Management channel clock Management channel serial data MCF5271 Pin ERXER EMDC EMDIO
The serial mode interface operates in what is generally referred to as AMD mode. The MCF5271 configuration for seven-wire serial mode connections to the external transceiver are shown in Table 5.
Table 5. Seven-Wire Mode Configuration
Signal Description Transmit clock Transmit enable Transmit data Collision Receive clock Receive enable Receive data Unused, configure as PB14 Unused input, tie to ground Unused, configure as PB[13:11] Unused output, ignore Unused, configure as PB[10:8] Unused, configure as PB15 Input after reset, connect to ground MCF5271 Pin ETXCLK ETXEN ETXD[0] ECOL ERXCLK ERXDV ERXD[0] ERXER ECRS ERXD[3:1] ETXER ETXD[3:1] EMDC EMDIO
Refer to the M5271EVB evaluation board user's manual for an example of how to connect an external PHY. Schematics for this board are accessible at the MCF5271 site by navigating to: http://www.freescale.com/coldfire.
5.7.3
BDM
Use the BDM interface as shown in the M5271EVB evaluation board user's manual. The schematics for this board are accessible at the Freescale website at: http://www.freescale.com/coldfire.
6
Mechanicals/Pinouts and Part Numbers
This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5271 devices. See Table 4 for a list the signal names and pin locations for each device.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 12 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Mechanicals/Pinouts and Part Numbers
6.1
1 A VSS
Pinout--196 MAPBGA
2 ETXCLK 3 ETXD3 4 ETXD2 5 QSPI_ DOUT 6 QSPI_CS0 7 U2RXD 8 U2TXD 9 CS3 10 CS6 11 CS4 12 A20 13 A17 14 VSS A
The following figure shows a pinout of the MCF5270/71CVMxxx package.
B
ERXD0
ERXER
ETXER
ETXD0
QSPI_DIN
BS3
QSPI_CS1
U1CTS
CS7
CS1
A23
A19
A16
A15
B
C
ERXD2
ERXD1
ETXEN
ETXD1
QSCK
BS2
BS0
RTS1
CS2
CS5
A22
A18
A14
A13
C
D
ERXCLK
ERXDV
ERXD3
EMDC
EMDIO
Core VDD_4
BS1
U1RXD1
U1TXD
CS0
A21
A12
A11
A10
D
E
ECRS
ECOL
NC
TIN0
VDD
VSS
VDD
SD_CKE
VSS
VDD
A9
A8
A7
A6
E
F
U0TXD
U0RXD
U0CTS
DTOUT0
TEST
VSS
VDD
VSS
VDD
VSS
Core VDD_3
A5
A4
A3
F
G
D31
D30
U0RTS
Core VDD_1
CLK MOD1 CLK MOD0
VDD
VSS
VDD
VSS
NC
A2
A1
A0
DTOUT3
G
H
D29
D28
D27
D26
VSS
VDD
VDD
VDD
NC
TA
TIP
TS
DTIN3
H
J
D25
D24
D23
D22
VSS
VDD
VSS
VDD
VSS
VDD
I2C_SCL
I2C_SDA
R/W
TEA
J
K
D21
D20
D19
D18
VDD
VDD
VSS
VDD
JTAG_EN
RCON
SD_ RAS
SD_ CAS
SD_ WE
CLKOUT
K
L
D17
D16
D10
Core VDD_2
D3
DTIN1
IRQ5
IRQ1
DTOUT2
PST0
DDATA0
SD_ CS1
SD_ CS0
VSSPLL
L
M
D15
D13
D9
D6
D2
DTOUT1
IRQ6
IRQ2
DTIN2
TDI/DSI
PST3
DDATA3
VDDPLL
EXTAL
M
N
D14
D12
D8
D5
D1
OE
IRQ7
IRQ3
TRST/ DSCLK TCLK/ PSTCLK 9
TDO/DSO
PST2
DDATA2
RESET
XTAL
N
P
VSS 1
D11 2
D7 3
D4 4
D0 5
TSIZ1 6
TSIZ0 7
IRQ4 8
TMS/ BKPT 10
PST1 11
DDATA1 12
RSTOUT 13
VSS 14
P
Figure 3. MCF5270/71CVMxxx Pinout (196 MAPBGA)
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 13
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Mechanicals/Pinouts and Part Numbers
6.2
Package Dimensions--196 MAPBGA
Figure 4 shows MCF5270/71CVMxxx package dimensions.
X Y D
Laser mark for pin 1 identification in this area
M K
NOTES: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package.
E Millimeters DIM Min A A1 A2 M TOL 13X e S
14 13 12 11 10 9 6 5 4 3 2 1 A B C D E F G H J K L M N P 1.25 0.27
Max
1.60 0.47
1.16 REF 0.45 0.55
b D E
15.00 BSC 15.00 BSC 1.00 BSC 0.50 BSC
Metalized mark for pin 1 identification in this area
e S
5 A A2 0.20 Z
S 13X e
A1
Z
4
0.10 Z 196X
Detail K Rotated 90 Clockwise
3 196X b 0.15 Z X Y 0.08 Z View M-M
Figure 4. 196 MAPBGA Package Dimensions (Case No. 1128A-01)
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 14 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
6.3
O-VDD ERXD0 ERXD1 ERXD2 ERXD3 ERXDV ERXCLK ECRS ECOL U0TIN U0TOUT U0CTS U0RXD U0TXD U0RTS Core VDD_1 VSS O-VDD TEST CLKMOD1 CLKMOD0 DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 VSS O-VDD DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 5 shows a pinout of the MCF5271CABxxx package.
Freescale Semiconductor
Pinout--160 QFP
MCF5271
Figure 5. MCF5270/71CABxxx Pinout (160 QFP)
O-VDD DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 Core Vdd_2 VSS O-VDD DATA4 DATA3 DATA2 DATA1 DATA0 DTIN1 OE IRQ7 IRQ4 IRQ1 DTIN2 VSS TCLK\PSTCLK O-VDD TRST/DSCLK TMS\BKPT TDO/DSO TDI/DSI PST0 PST1 PST2 PST3 JTAG_EN RCON VSS 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
VSS ERXER ETXCLK ETXEN ETXER ETXD3 ETXD2 ETXD1 ETXD0 EMDC EMDIO QSPI_DOUT QSPI_DIN QSPI_CLK QSPI_CS0 O-VDD VSS BS3 BS2 BS1 BS0 QSPI_CS1/SD_CKE O-VDD VSS U1CTS U1RTS U1RXD U1TXD CS3 CS2 CS1 CS0 O-VDD VSS A23 A18 A21 A20 A19 A18
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4
A17 A16 A15 A14 A13 A12 O-VDD VSS A11 A10 A9 A8 A7 A6 A5 O-VDD VSS Core_Vdd_3 A4 A3 A2 A1 A0 TS TA R/W O-VDD VSS SD_WE SD_SCAS SD_SRAS CLKOUT VSS VDDPLL EXTAL XTAL VSSPLL RESET RSTOUT O-VDD
Mechanicals/Pinouts and Part Numbers
15
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Mechanicals/Pinouts and Part Numbers
6.4
Package Dimensions--160 QFP
Figure 6 shows MCF5270/71CAB80 package dimensions.
Y L
-A-, -B-, -D-
M
A-B
-A- L
H
B
V
0.20 (0.008)
0.20 (0.008)
0.20 (0.008) M
H
-B-
B
B
P G DETAIL A
DETAIL A
Z A
0.20 (0.008) M C 0.20 (0.008) A-B A-B
S
DS
BASE METAL
S
0.20 (0.008) MC A-B
S
N
DS
J F D
DETAIL C
0.13 (0.005) M
-H-
C A-B
S
DS
SECTION B-B
MILLIMETERS DIM MIN MAX A 27.90 28.10 27.90 28.10 B 3.35 3.85 C D 0.22 0.38 3.20 3.50 E 0.22 0.33 F 0.65 BSC G H 0.25 0.35 J 0.11 0.23 K 0.70 0.90 25.35 BSC L 16 M 5 0.11 0.19 N 0.325 BSC P Q 7 0 R 0.13 0.30 S 31.00 31.40 0.13 -- T U -- 0 V 31.00 31.40 0.4 -- W 1.60 REF X Y 1.33 REF 1.33 REF Z INCHES MIN MAX 1.098 1.106 1.098 1.106 0.132 1.106 0.009 0.015 0.126 0.138 0.009 0.013 0.026 REF 0.010 0.014 0.004 0.009 0.028 0.035 0.998 REF 5 16 0.004 0.007 0.013 REF 0 7 0.005 0.012 1.220 1.236 0.005 -- 0 -- 1.220 1.236 0.016 -- 0.063 REF 0.052 REF 0.052 REF
M
x
NOTES 1. DIMENSIONING AND TOLERINCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DATUM PLAN -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B-, AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
TOP & BOTTOM
Ux C E -H-
T R Qx
-C- H
W K X
0.110 (0.004)
DETAIL C
Case 864A-03
Figure 6. 160 QFP Package Dimensions
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 16 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
DS
A-B S
A-B S
DS
Electrical Characteristics
6.5
Ordering Information
Table 6. Orderable Part Numbers
Description MCF5270 RISC Microprocessor MCF5270 RISC Microprocessor MCF5270 RISC Microprocessor MCF5270 RISC Microprocessor MCF5271 RISC Microprocessor MCF5271 RISC Microprocessor MCF5271 RISC Microprocessor Package 160 QFP 160 QFP 196 MAPBGA 196 MAPBGA 160 QFP 196 MAPBGA 196 MAPBGA Speed 100MHz 100MHz 100MHz 150MHz 100MHz 100MHz 150MHz Lead-Free? Yes Yes Yes Yes Yes Yes Yes Temperature 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
Freescale Part Number MCF5270AB100 MCF5270CAB100 MCF5270VM100 MCF5270CVM150 MCF5271CAB100 MCF5271CVM100 MCF5271CVM150
7
Electrical Characteristics
This chapter contains electrical specification tables and reference timing diagrams for the MCF5271 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5271. NOTE The parameters specified in this processor document supersede any values found in the module specifications.
7.1
Maximum Ratings
Table 7. Absolute Maximum Ratings1, 2
Rating Core Supply Voltage Pad Supply Voltage PLL Supply Voltage Digital Input Voltage
3
Symbol VDD OVDD VDDPLL VIN ID TA (TL - TH) Tstg
Value - 0.5 to +2.0 - 0.3 to +4.0 - 0.3 to +4.0 - 0.3 to + 4.0 25 - 40 to 85 - 65 to 150
Unit V V V V mA C C
Instantaneous Maximum Current Single pin limit (applies to all pins) 3,4,5 Operating Temperature Range (Packaged) Storage Temperature Range
1
Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 17
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Electrical Characteristics
2
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or OVDD). 3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 All functional non-supply pins are internally clamped to VSS and OVDD. 5 Power supply must maintain regulation within operating OVDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > OVDD) is greater than IDD, the injection current may flow out of OVDD and could result in external power supply going out of regulation. Insure external OVDD load will shunt current greater than maximum injection current. This will be the greatest risk when the processor is not consuming power (ex; no clock).Power supply must maintain regulation within operating OVDD range during instantaneous and operating maximum current conditions.
7.2
Thermal Characteristics
Table 8. Thermal Characteristics
Characteristic Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature
1
The below table lists thermal resistance values.
Symbol Four layer board (2s2p) Four layer board (2s2p) JMA JMA JB JC jt Tj
196 160QFP MAPBGA 321,2 291,2 203 104 21,5 104 401,2 361,2 253 104 21,5 105
Unit C/ W C/ W C/ W C/ W C/ W
oC
2 3 4 5
JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Motorola recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in C can be obtained from:
T J = T A + ( P D x JMA ) (1)
Where:
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 18 Freescale Semiconductor
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Electrical Characteristics
TA= Ambient Temperature, C JMA= Package Thermal Resistance, Junction-to-Ambient, C/W PD= PINT + PI/O PINT= IDD x VDD, Watts - Chip Internal Power PI/O= Power Dissipation on Input and Output Pins -- User Determined For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
P D = K / ( T J + 273C ) (2)
Solving equations 1 and 2 for K gives:
K = PD x (TA + 273 C) + JMA x PD 2 (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
7.3
DC Electrical Specifications
Table 9. DC Electrical Specifications1
Characteristic Symbol VDD OVDD VDDPLL VIH VIL VHYS Iin IOZ VOH VOL IAPU Cin -- -- Min 1.4 3.0 3.0 0.7 x OVDD VSS - 0.3 0.06 x OVDD -1.0 -1.0 OVDD - 0.5 -- -10 Typical -- -- -- -- -- -- -- -- -- -- -- -- 7 7 Max 1.6 3.6 3.6 3.65 0.35 x OVDD -- 1.0 1.0 -- 0.5 - 130 Unit V V V V V mV A A V V A pF
Core Supply Voltage Pad Supply Voltage PLL Supply Voltage Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Vin = VDD or VSS, Input-only pins High Impedance (Off-State) Leakage Current Vin = VDD or VSS, All input/output and output pins Output High Voltage (All input/output and all output pins) IOH = -5.0 mA Output Low Voltage (All input/output and all output pins) IOL = 5.0mA Weak Internal Pull Up Device Current, tested at VIL Max.2 Input Capacitance 3 All input-only pins All input/output (three-state) pins
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 19
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Electrical Characteristics
Table 9. DC Electrical Specifications1 (continued)
Characteristic Load Capacitance4 Low drive strength High drive strength Core Operating Supply Current 5 Master Mode Pad Operating Supply Current Master Mode Low Power Modes DC Injection Current 3, 6, 7, 8 VNEGCLAMP =VSS- 0.3 V, VPOSCLAMP = VDD + 0.3 Single Pin Limit Total processor Limit, Includes sum of all stressed pins
1 2 3 4
Symbol CL IDD
Min
Typical -- --
Max 25 50 150 -- --
Unit pF pF mA mA A
-- OIDD -- -- IIC -1.0 -10
135 100 TBD
1.0 10
mA mA
5 6 7 8
Refer to Table 10 for additional PLL specifications. Refer to the MCF5271 signals section for pins having weak internal pull-up devices. This parameter is characterized before qualification rather than 100% tested. pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require transmission line analysis to determine proper drive strength and termination. See High Speed Signal Propagation: Advanced Black Magic by Howard W. Johnson for design guidelines. Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. All functional non-supply pins are internally clamped to VSS and their respective VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the processor is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not present during the power-up sequence until the PLL has attained lock.
7.4
Oscillator and PLLMRFM Electrical Characteristics
Table 10. HiP7 PLLMRFM Electrical Specifications1
Num 1 Characteristic PLL Reference Frequency Range Crystal reference External reference 1:1 mode (NOTE: fsys/2 = 2 x fref_1:1) Core frequency CLKOUT Frequency 2 External reference On-Chip PLL Frequency Loss of Reference Frequency 3, 5 Self Clocked Mode Frequency Crystal Start-up Time 5, 6
4, 5
Symbol
Min. Value
Max. Value
Unit MHz
fref_crystal fref_ext fref_1:1 fsys fsys/2 fLOR fSCM tcst
8 8 24 0 fref / 32 100 10.25 --
25 25 75 150 75 75 1000 15.25 10 MHz MHz MHz kHz MHz ms
2
3 4 5
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 20 Freescale Semiconductor
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Electrical Characteristics
Table 10. HiP7 PLLMRFM Electrical Specifications1 (continued)
Num 6 7 8 Characteristic XTAL Load Capacitance5 PLL Lock Time
5, 7,13
Symbol
Min. Value 5
Max. Value 30 750 11 750 1 60 4.1 2.0 5.0 .01
Unit pF s ms s ns % % fsys/2 % fsys/2 % fsys/2
tlpll tlplk
-- -- --
Power-up To Lock Time 5, 6,8 With Crystal Reference (includes 5 time) Without Crystal Reference9 1:1 Mode Clock Skew (between CLKOUT and EXTAL) 10 Duty Cycle of reference 5 Frequency un-LOCK Range Frequency LOCK Range CLKOUT Period Jitter, 5, 6, 8,11, 12 Measured at fsys/2 Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter (Averaged over 2 ms interval) Frequency Modulation Range Limit13,14 (fsys/2 Max must not be exceeded) ICO Frequency. fico = fref x 2 x (MFD+2) 15
9 10 11 12 13
tskew tdc fUL fLCK Cjitter
-1 40 -3.8 -1.7 -- --
14 15
1 2 3 4 5 6 7 8
Cmod fico
0.8 48
2.2 150
%fsys/2 MHz
9 10 11
12 13 14 15
All values given are initial design targets and subject to change. All internal registers retain data at 0 Hz. "Loss of Reference Frequency" is the reference frequency detected internally, which transitions the PLL into self clocked mode. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR with default MFD/RFD settings. This parameter is guaranteed by characterization before qualification rather than 100% tested. Proper PC board layout procedures must be followed to achieve specifications. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). Assuming a reference is available at power up, lock time is measured from the time VDD and VDDSYN are valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must be added to the PLL lock time to determine the total start-up time. tlpll = (64 * 4 * 5 + 5 ) Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and = 1.57x10-6 2(MFD + 2). PLL is operating in 1:1 PLL mode. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod. Modulation percentage applies over an interval of 10s, or equivalently the modulation rate is 100KHz. Modulation rate selected must not result in fsys/2 value greater than the fsys/2 maximum specified value. Modulation range determined by hardware design. fsys/2 = fico / (2 * 2RFD)
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 21
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Electrical Characteristics
7.5
External Interface Timing Characteristics
NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the CLKOUT output. All other timing relationships can be derived from these values.
Table 11. Processor Bus Input Timing Specifications
Name freq B0 System bus frequency CLKOUT period Control Inputs B1a B1b B2a B2b Control input valid to CLKOUT high2 BKPT valid to CLKOUT high3 CLKOUT high to control inputs invalid2 CLKOUT high to asynchronous control input BKPT invalid3 tCVCH tBKVCH tCHCII tBKNCH 9 9 0 0 -- -- -- -- ns ns ns ns Characteristic1 Symbol fsys/2 tcyc Min 50 -- Max 75 1/75 Unit MHz ns
Table 11 lists processor bus input timings.
Data Inputs B4 B5
1
Data input (D[31:0]) valid to CLKOUT high CLKOUT high to data input (D[31:0]) invalid
tDIVCH tCHDII
4 0
-- --
ns ns
Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line environment.. 2 TEA and TA pins are being referred to as control inputs. 3 Refer to figure A-19.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 22 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Electrical Characteristics
Timings listed in Table 11 are shown in Figure 7.
* The timings are also valid for inputs sampled on the negative clock edge. CLKOUT(75MHz) TSETUP THOLD 1.5V
Input Setup And Hold
Invalid
1.5V Valid 1.5V
Invalid
trise Input Rise Time Vh = VIH Vl = VIL
tfall Input Fall Time Vh = VIH Vl = VIL
CLKOUT
B4 B5
Inputs
Figure 7. General Input Timing Requirements
7.6
Processor Bus Output Timing Specifications
Table 12. External Bus Output Timing Specifications
Name Characteristic Control Outputs B6a B6b B6c B7 B7a CLKOUT high to chip selects valid 1 CLKOUT high to byte enables (BS[3:0]) valid2 CLKOUT high to output enable (OE) valid3 CLKOUT high to control output (BS[3:0], OE) invalid CLKOUT high to chip selects invalid tCHCV tCHBV tCHOV tCHCOI tCHCI -- -- -- 0.5tCYC+1.5 0.5tCYC+1.5 0.5tCYC +5 0.5tCYC +5 0.5tCYC +5 -- -- ns ns ns ns ns Symbol Min Max Unit
Table 12 lists processor bus output timings.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 23
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Electrical Characteristics
Table 12. External Bus Output Timing Specifications (continued)
Name Characteristic Symbol Min Max Unit
Address and Attribute Outputs B8 B9 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) valid CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) invalid Data Outputs B11 B12 B13
1 2 3
tCHAV tCHAI
-- 1.5
9 --
ns ns
CLKOUT high to data output (D[31:0]) valid CLKOUT high to data output (D[31:0]) invalid CLKOUT high to data output (D[31:0]) high impedance
tCHDOV tCHDOI tCHDOZ
-- 1.5 --
9 -- 9
ns ns ns
CS transitions after the falling edge of CLKOUT. BS transitions after the falling edge of CLKOUT. OE transitions after the falling edge of CLKOUT.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 24 Freescale Semiconductor
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Electrical Characteristics
Read/write bus timings listed in Table 12 are shown in Figure 8, Figure 9, and Figure 10.
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT B7a CSn A[23:0] TSIZ[1:0] B8 TS TIP B8 B6c OE B7 B9 R/W (H) B6b BS[3:0] B4 D[31:0] B5 TA (H) B13 B7 B11 B12 B8 B6b B7 B0 B9 B8 B9 B9 B7a B6a B8 B9
B6a
B8
TEA (H)
Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 25
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Electrical Characteristics
Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 12.
S0 CLKOUT B6a CSn B8 A[23:0] TSIZ[1:0] B8 TS B8 TIP B6c OE B7 B9 B9
B7a
S1
S2
S3
S4
S5
S0
S1
B9
R/W (H) B6b BS[3:0] B4 D[31:0] B2a TA B1a TEA (H) B7 B5
Figure 9. SRAM Read Bus Cycle Terminated by TA
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 26 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Electrical Characteristics
Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 12.
S0
CLKOUT B6a CSn B8 A[23:0] TSIZ[1:0] B8 TS B8 TIP B6c OE B7 B9 B9 B9 B7a S1 S2 S3 S4 S5 S0 S1
R/W (H) B6b BS[3:0] B7
D[31:0]
TA (H)
B1a TEA B2a
Figure 10. SRAM Read Bus Cycle Terminated by TEA
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 27
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Electrical Characteristics
Figure 11 shows an SDRAM read cycle.
0 SD_CKE
D1 D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A[23:0]
D2
Row
Column
D4
D4
SD_SRAS
D2
SD_CAS1
D4 D2 D4
SDWE
D5
D[31:0]
D2 D6
RAS[1:0]
CAS[3:0]
ACTV 1 NOP READ NOP NOP PALL
DACR[CASL] = 2
Figure 11. SDRAM Read Cycle Table 13. SDRAM Timing
NUM D1 D2 D3 D4 D5 D6 D71 D81
1
Characteristic CLKOUT high to SDRAM address valid CLKOUT high to SDRAM control valid CLKOUT high to SDRAM address invalid CLKOUT high to SDRAM control invalid SDRAM data valid to CLKOUT high CLKOUT high to SDRAM data invalid CLKOUT high to SDRAM data valid CLKOUT high to SDRAM data invalid
Symbol tCHDAV tCHDCV tCHDAI tCHDCI tDDVCH tCHDDI tCHDDVW tCHDDIW
Min -- -- 1.5 1.5 4 1.5 -- 1.5
Max 9 9 -- -- -- -- 9 --
Unit ns ns ns ns ns ns ns ns
D7 and D8 are for write cycles only.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 28 Freescale Semiconductor
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Electrical Characteristics
Figure 12 shows an SDRAM write cycle.
0 SD_CKE
D1 D3
1
2
3
4
5
6
7
8
9
10
11
12
A[23:0]
D2
Row
Column
D4
SD_SRAS
D2
SD_SCAS1
D4
SD_WE
D7
D[31:0]
D2 D8
RAS[1:0]
D2 D4
CAS[3:0]
ACTV 1 DACR[CASL] NOP WRITE NOP PALL
=2
Figure 12. SDRAM Write Cycle
7.7
NUM G1 G2 G3 G4
1
General Purpose I/O Timing
Table 14. GPIO Timing1
Characteristic CLKOUT High to GPIO Output Valid CLKOUT High to GPIO Output Invalid GPIO Input Valid to CLKOUT High CLKOUT High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.5 9 1.5 Max 10 -- -- -- Unit ns ns ns ns
GPIO pins include: INT, UART, Timer, DREQn and DACKn pins.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 29
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
CLKOUT G1 GPIO Outputs G2
G3 GPIO Inputs
G4
Figure 13. GPIO Timing
7.8
Reset and Configuration Override Timing
Table 15. Reset and Configuration Override Timing (VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM R1 R2 R3 R4 R5 R6 R7 R8
1 2
Characteristic RESET Input valid to CLKOUT High CLKOUT High to RESET Input invalid RESET Input valid Time
2
Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ
Min 9 1.5 5 -- 0 20 0 --
Max -- -- -- 10 -- -- -- 1
Unit ns ns tCYC ns ns tCYC ns tCYC
CLKOUT High to RSTOUT Valid RSTOUT valid to Config. Overrides valid Configuration Override Setup Time to RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid to Configuration Override High Impedance
All AC timing is shown with respect to 50% VDD levels unless otherwise noted. During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
CLKOUT
R1 R3 R2
RESET
R4 R4
RSTOUT
R8 R5 R6 R7
Configuration Overrides*: (RCON, Override pins])
Figure 14. RESET and Configuration Override Timing
Refer to the chip configuration module (CCM) chapter in the device's reference manual for more information.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 30 Freescale Semiconductor
Electrical Characteristics
7.9
I2C Input/Output Timing Specifications
Table 16. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num I1 I2 I3 I4 I5 I6 I7 I8 I9 Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Characteristic Min 2 8 -- 0 -- 4 0 2 2 Max -- -- 1 -- 1 -- -- -- -- Units tcyc tcyc ms ns ms tcyc ns tcyc tcyc
Table 16 lists specifications for the I2C input timing parameters shown in Figure 15.
Table 17 lists specifications for the I2C output timing parameters shown in Figure 15.
Table 17. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num I11 I2 1 I3 2 I4 I5
1 3
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 6 10 -- 7 -- 10 2 20 10
Max -- -- -- -- 3 -- -- -- --
Units tcyc tcyc s tcyc ns tcyc tcyc tcyc tcyc
I6 1 I7 1 I8 I9
1 1 1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 17. The I2C interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 17 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
Figure 15 shows timing for the values in Table 16 and Table 17.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 31
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Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
I2
I6
I5
I2C_SCL I1 I4 I7 I8
I3
I9
I2C_SDA
Figure 15. I2C Input/Output Timings
7.10
Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
7.10.1
MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the ERXCLK frequency. Table 18 lists MII receive channel timings.
Table 18. MII Receive Signal Timing
Num M1 M2 M3 M4 Characteristic ERXD[3:0], ERXDV, ERXER to ERXCLK setup ERXCLK to ERXD[3:0], ERXDV, ERXER hold ERXCLK pulse width high ERXCLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns ERXCLK period ERXCLK period
Figure 16 shows MII receive signal timings listed in Table 18.
M3
ERXCLK (input)
ERXD[3:0] (inputs) ERXDV ERXER
M1 M2
M4
Figure 16. MII Receive Signal Timing Diagram
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 32 Freescale Semiconductor
Electrical Characteristics
7.10.2
MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)
Table 19 lists MII transmit channel timings. The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the ETXCLK frequency.
Table 19. MII Transmit Signal Timing
Num M5 M6 M7 M8 Characteristic ETXCLK to ETXD[3:0], ETXEN, ETXER invalid ETXCLK to ETXD[3:0], ETXEN, ETXER valid ETXCLK pulse width high ETXCLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns ETXCLK period ETXCLK period
Figure 17 shows MII transmit signal timings listed in Table 19.
M7
ETXCLK (input)
M5
ETXD[3:0] (outputs) ETXEN ETXER
M6
M8
Figure 17. MII Transmit Signal Timing Diagram
7.10.3
MII Async Inputs Signal Timing (ECRS and ECOL)
Table 20. MII Async Inputs Signal Timing
Table 20 lists MII asynchronous inputs signal timing.
Num M9
Characteristic ECRS, ECOL minimum pulse width
Min 1.5
Max --
Unit ETXCLK period
Figure 18 shows MII asynchronous input timings listed in Table 20.
ECRS, ECOL M9
Figure 18. MII Async Inputs Timing Diagram
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 33
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Electrical Characteristics
7.10.4
MII Serial Management Channel Timing (EMDIO and EMDC)
Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 21. MII Serial Management Channel Timing
Num M10 M11 M12 M13 M14 M15 Characteristic EMDC falling edge to EMDIO output invalid (minimum propagation delay) EMDC falling edge to EMDIO output valid (max prop delay) EMDIO (input) to EMDC rising edge setup EMDIO (input) to EMDC rising edge hold EMDC pulse width high EMDC pulse width low Min 0 -- 10 0 Max -- 25 -- -- Unit ns ns ns ns
40% 60% MDC period 40% 60% MDC period
Figure 19 shows MII serial management channel timings listed in Table 21.
M14 M15
EMDC (output)
M10
EMDIO (output)
M11
EMDIO (input)
M12
M13
Figure 19. MII Serial Management Channel Timing Diagram
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 34 Freescale Semiconductor
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Electrical Characteristics
7.11
32-Bit Timer Module AC Timing Specifications
Table 22. Timer Module AC Timing Specifications
0-66 MHz Name T1 T2 Characteristic Min DT0IN / DT1IN / DT2IN / DT3IN cycle time DT0IN / DT1IN / DT2IN / DT3IN pulse width 3 1 Max -- -- tCYC tCYC Unit
Table 22 lists timer module AC timings.
7.12
QSPI Electrical Specifications
Table 23. QSPI Modules AC Timing Specifications
Table 23 lists QSPI timings.
Name QS1 QS2 QS3 QS4 QS5 QSPI_CS[1:0] to QSPI_CLK
Characteristic
Min 1 -- 2 9 9
Max 510 10 -- -- --
Unit tcyc ns ns ns ns
QSPI_CLK high to QSPI_DOUT valid. QSPI_CLK high to QSPI_DOUT invalid. (Output hold) QSPI_DIN to QSPI_CLK (Input setup) QSPI_DIN to QSPI_CLK (Input hold)
The values in Table 23 correspond to Figure 20.
QS1
QSPI_CS[1:0]
QSPI_CLK
QS2
QSPI_DOUT
QS3 QS4 QS5
QSPI_DIN
Figure 20. QSPI Timing
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 35
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Electrical Characteristics
7.13
JTAG and Boundary Scan Timing
Table 24. JTAG and Boundary Scan Timing
Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 4 26 0 4 26 0 0 4 10 0 0 100 10 Max 1/4 -- -- 3 -- -- 33 33 -- -- 26 8 -- -- Unit fsys/2 tCYC ns ns ns ns ns ns ns ns ns ns ns ns
1
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2 J3 J3
TCLK (input)
J4
VIH VIL J4
Figure 21. Test Clock Input Timing
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 36 Freescale Semiconductor
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Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages 37
TCLK
VIL J5
VIH J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 22. Boundary Scan (JTAG) Timing
TCLK
VIL J9
VIH J10
TDI TMS
J11
Input Data Valid
TDO
J12
Output Data Valid
TDO
J11
TDO
Output Data Valid
Figure 23. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 24. TRST Timing
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor
Electrical Characteristics
7.14
Debug AC Timing Specifications
Table 25. Debug AC Timing Specification
150 MHz Num DE0 DE1 DE2 DE3 DE4 DE51 DE6 DE7
1
Table 25 lists specifications for the debug AC timing parameters shown in Figure 26.
Characteristic Min PSTCLK cycle time PST valid to PSTCLK high PSTCLK high to PST invalid DSCLK cycle time DSI valid to DSCLK high DSCLK high to DSO invalid BKPT input data setup time to CLKOUT rise CLKOUT high to BKPT high Z -- 4 1.5 5 1 4 4 0 Max 0.5 -- -- -- -- -- -- 10
Units tcyc ns ns tcyc tcyc tcyc ns ns
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT.
Figure 25 shows real-time trace timing for the values in Table 25.
PSTCLK
DE0 DE1 DE2
PST[3:0] DDATA[3:0]
Figure 25. Real-Time Trace AC Timing
Figure 26 shows BDM serial port AC timing for the values in Table 25.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 38 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
Documentation Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF527x products in 196 MAPBGA packages
CLKOUT DE6 BKPT DE7 DE5
DSCLK DE3 DSI Current DE4 DSO Past Current Next
Figure 26. BDM Serial Port AC Timing
8
Documentation
Documentation regarding the MCF5271 and their development support tools is available from a local Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or through the Freescale web address at http://www.freescale.com/coldfire.
9
Document Revision History
Table 26. MCF5271EC Revision History
Rev. No. 0 1 1.1 1.2 Initial release * Fixed several clock values. * Updated Signal List table * Removed duplicate information in the module description sections. The information is all in the Signals Description Table. * Removed detailed signal description section. This information can be found in the MCF5271RM Chapter 2. * Removed detailed feature list. This information can be found in the MCF5271RM Chapter 1. * Changed instances of Motorola to Freescale * Added values for `Maximum operating junction temperature' in Table 8. * Added typical values for `Core operating supply current (master mode)' in Table 9. * Added typical values for `Pad operating supply current (master mode)' in Table 9. * Removed unnecessary PLL specifications, #6-9, in Table 10. Substantive Change(s)
The below table provides a revision history for this document.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 39
Document Revision History
Table 26. MCF5271EC Revision History (continued)
Rev. No. 1.3 Substantive Change(s) * Device is now available in 150 MHz versions. Updated specs where necessary to reflect this improvement. * Added 2 new part numbers to Table 6: MCF5270CVM150 and MCF5271CVM150. * Removed features list. This information can be found in the MCF5271RM. * Removed SDRAM address multiplexing section. This information can be found in the MCF5271RM. * Added Section 5.2.1, "Supply Voltage Sequencing and Separation Cautions." * Updated 196MAPBGA package dimensions, Figure 4. * * * * * * Table 2: Changed SD_CKE pin location from 139 to "--" for the 160QFP device. Table 2: Changed QSPI_CS1 pin location from "--" to 139 for the 160QFP device. Table 2: Changed DT3IN pin's alternate 2 function from "--" to QSPI_CS2. Table 2: Changed DT3OUT pin's alternate 2 function from "--" to QSPI_CS3. Figure 5: Changed pin 139 label from "SD_CKE/QSPI_CS1" to "QSPI_CS1/SD_CKE". Removed second sentence from Section 7.10.1, "MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)," and Section 7.10.2, "MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)," regarding no minimum frequency requirement for TXCLK. * Removed third and fourth paragraphs from Section 7.10.2, "MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)," as this feature is not supported on this device.
1.4 2
3
* Section 5.2.1, "Supply Voltage Sequencing and Separation Cautions" changed PLLVDD to VDDPLL to match rest of document. * Section 5.2.1, "Supply Voltage Sequencing and Separation Cautions" Changed VDDPLL voltage level from 1.5V to 3.3V throughout section. * Section 5.2.1.1, "Power Up Sequence" first bullet, changed "Use 1 s" to "Use 1 ms". * Corrected position of spec D5 in Figure 11. * Figure 3: Corrected M4 ball location from DATA5 to DATA6, changed DATAn labels to Dn for consistency * Table 14: Added DACKn and DREQn to footnote. * Table 9, added PLL supply voltage row * Added part number MCF5270CAB100 in Table 6
4
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 40 Freescale Semiconductor
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Freescale Semiconductor Document Revision History
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4
41
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Rev. 4 08/2009
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